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82 lines
2.4 KiB
Verilog
82 lines
2.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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enum integer {
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EP_State_IDLE ,
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EP_State_CMDSHIFT0 ,
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EP_State_CMDSHIFT13 ,
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EP_State_CMDSHIFT14 ,
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EP_State_CMDSHIFT15 ,
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EP_State_CMDSHIFT16 ,
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EP_State_DWAIT ,
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EP_State_DSHIFT0 ,
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EP_State_DSHIFT1 ,
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EP_State_DSHIFT15 } m_state_xr, m_state2_xr;
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// Beginning of automatic ASCII enum decoding
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reg [79:0] m_stateAscii_xr; // Decode of m_state_xr
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always @(m_state_xr) begin
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case ({m_state_xr})
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EP_State_IDLE: m_stateAscii_xr = "idle ";
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EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 ";
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EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13";
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EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14";
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EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15";
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EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16";
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EP_State_DWAIT: m_stateAscii_xr = "dwait ";
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EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 ";
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EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 ";
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EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 ";
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default: m_stateAscii_xr = "%Error ";
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endcase
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end
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// End of automatics
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
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if (cyc==1) begin
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m_state_xr <= EP_State_IDLE;
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m_state2_xr <= EP_State_IDLE;
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end
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if (cyc==2) begin
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if (m_stateAscii_xr != "idle ") $stop;
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m_state_xr <= EP_State_CMDSHIFT13;
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if (m_state2_xr != EP_State_IDLE) $stop;
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m_state2_xr <= EP_State_CMDSHIFT13;
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end
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if (cyc==3) begin
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if (m_stateAscii_xr != "cmdshift13") $stop;
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m_state_xr <= EP_State_CMDSHIFT16;
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if (m_state2_xr != EP_State_CMDSHIFT13) $stop;
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m_state2_xr <= EP_State_CMDSHIFT16;
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end
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if (cyc==4) begin
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if (m_stateAscii_xr != "cmdshift16") $stop;
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m_state_xr <= EP_State_DWAIT;
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if (m_state2_xr != EP_State_CMDSHIFT16) $stop;
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m_state2_xr <= EP_State_DWAIT;
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end
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if (cyc==9) begin
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if (m_stateAscii_xr != "dwait ") $stop;
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if (m_state2_xr != EP_State_DWAIT) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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