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169 lines
7.5 KiB
Verilog
169 lines
7.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t;
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reg [40:0] quad; initial quad = 41'ha_bbbb_cccc;
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reg [80:0] wide; initial wide = 81'habc_1234_5678_1234_5678;
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reg [8:0] nine; initial nine = 12;
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reg signed [40:0] quads; initial quads = -(41'sha_bbbb_cccc);
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reg signed [80:0] wides; initial wides = -(81'shabc_1234_5678_1234_5678);
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reg signed [8:0] nines; initial nines = -12;
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reg [31:0] str; initial str = "\000\277\021\n";
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reg [47:0] str2; initial str2 = "\000what!";
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reg [79:0] str3; initial str3 = "\000hmmm!1234";
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string svs = "sv-str";
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sub sub ();
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sub2 sub2 ();
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initial begin
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$write("[%0t] In %m: Hi\n", $time);
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sub.write_m;
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sub2.write_m;
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// Escapes
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$display("[%0t] Back \\ Quote \"", $time); // Old bug when \" last on the line.
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// Display formatting - constants
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$display("[%0t] %%b=%b %%0b=%0b %%b=%b %%0b=%0b %%b=%b %%0b=%0b", $time,
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9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
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81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
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$display("[%0t] %%B=%B %%0B=%0B %%B=%B %%0B=%0B %%B=%B %%0B=%0B", $time,
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9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
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81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
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$display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time,
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9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
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81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
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$display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time,
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9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
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81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
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$display("[%0t] %%h=%h %%0h=%0h %%h=%h %%0h=%0h %%h=%h %%0h=%0h", $time,
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9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
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81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
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$display("[%0t] %%H=%H %%0H=%0H %%H=%H %%0H=%0H %%H=%H %%0H=%0H", $time,
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9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
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81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
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$display("[%0t] %%o=%o %%0o=%0o %%o=%o %%0o=%0o %%o=%o %%0o=%0o", $time,
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9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
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81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
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$display("[%0t] %%O=%O %%0O=%0O %%O=%O %%0O=%0O %%O=%O %%0O=%0o", $time,
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9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
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81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
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$display("[%0t] %%x=%x %%0x=%0x %%x=%x %%0x=%0x %%x=%x %%0x=%0x", $time,
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9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
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81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
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$display("[%0t] %%X=%X %%0X=%0X %%X=%X %%0X=%0X %%X=%X %%0X=%0X", $time,
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9'd12, 9'd12, 41'habbbbcccc, 41'habbbbcccc,
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81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
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$display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time,
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9'sd12, 9'sd12, -(41'shabbbbcccc), -(41'shabbbbcccc),
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81'habc_1234_5678_1234_5678, 81'habc_1234_5678_1234_5678);
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$display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time,
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9'sd12, 9'sd12, -(41'shabbbbcccc), -(41'shabbbbcccc),
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-(81'shabc_1234_5678_1234_5678), -(81'shabc_1234_5678_1234_5678));
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// Display formatting
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$display("[%0t] %%b=%b %%0b=%0b %%b=%b %%0b=%0b %%b=%b %%0b=%0b", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%B=%B %%0B=%0B %%B=%B %%0B=%0B %%B=%B %%0B=%0B", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%h=%h %%0h=%0h %%h=%h %%0h=%0h %%h=%h %%0h=%0h", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%H=%H %%0H=%0H %%H=%H %%0H=%0H %%H=%H %%0H=%0H", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%o=%o %%0o=%0o %%o=%o %%0o=%0o %%o=%o %%0o=%0o", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%O=%O %%0O=%0O %%O=%O %%0O=%0O %%O=%O %%0O=%0o", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%x=%x %%0x=%0x %%x=%x %%0x=%0x %%x=%x %%0x=%0x", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%X=%X %%0X=%0X %%X=%X %%0X=%0X %%X=%X %%0X=%0X", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%d=%d %%0d=%0d %%d=%d %%0d=%0d %%d=%d %%0d=%0d", $time,
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nines, nines, quads, quads, wides, wides);
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$display("[%0t] %%D=%D %%0D=%0D %%D=%D %%0D=%0D %%D=%D %%0D=%0D", $time,
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nines, nines, quads, quads, wides, wides);
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//
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// verilator lint_off WIDTH
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$display("[%0t] %%C=%C %%0C=%0C", $time,
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"a"+nine, "a"+nine);
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$display("[%0t] %%c=%c %%0c=%0c", $time,
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"a"+nine, "a"+nine);
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// verilator lint_on WIDTH
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$display("[%0t] %%v=%v %%0v=%0v %%v=%v %%0v=%0v %%v=%v %%0v=%0v <", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%V=%V %%0V=%0V %%V=%V %%0V=%0V %%V=%V %%0V=%0V <", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%p=%p %%0p=%0p %%p=%p %%0p=%0p %%p=%p %%0p=%0p", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%P=%P %%0P=%0P %%P=%P %%0P=%0P %%P=%P %%0P=%0P", $time,
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nine, nine, quad, quad, wide, wide);
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$display("[%0t] %%P=%P", $time,
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svs);
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$display("[%0t] %%u=%u %%0u=%0u", $time,
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{"a","b","c","d"}, {"a","b","c","d"}); // Avoid binary output
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$display("[%0t] %%U=%U %%0U=%0U", $time,
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{"a","b","c","d"}, {"a","b","c","d"}); // Avoid binary output
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// %z is tested in t_sys_sformat.v
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$display("[%0t] %%D=%D %%d=%d %%01d=%01d %%06d=%06d %%6d=%6d", $time,
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nine, nine, nine, nine, nine);
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$display("[%0t] %%t=%t %%03t=%03t %%0t=%0t", $time,
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$time, $time, $time);
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$display;
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// Not testing %0s, it does different things in different simulators
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$display("[%0t] %%s=%s %%s=%s %%s=%s", $time,
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str2[7:0], str2, str3);
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$display("[%0t] %s%s%s", $time,
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"hel", "lo, fr", "om a very long string. Percent %s are literally substituted in.");
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$display("hel", "lo, fr", "om a concatenated string.");
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$write("hel", "lo, fr", "om a concatenated format string [%0t].\n", $time);
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$display("extra argument: ", $time);
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$display($time, ": pre argument");
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$write("[%0t] Embedded \r return\n", $time);
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$display("[%0t] Embedded\
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multiline", $time);
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// Str check
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`ifndef NC // NC-Verilog 5.3 chokes on this test
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if (str !== 32'h00_bf_11_0a) $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub;
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task write_m;
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begin
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$write("[%0t] In %m (%l)\n", $time);
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begin : subblock
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$write("[%0t] In %M (%L)\n", $time); // Uppercase %M test
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end
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end
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endtask
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endmodule
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module sub2;
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// verilator no_inline_module
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task write_m;
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begin
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$write("[%0t] In %m (%l)\n", $time);
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begin : subblock2
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$write("[%0t] In %m (%L)\n", $time);
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end
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end
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endtask
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endmodule
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