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verilator/test_regress/t/t_cover_line_trace.out
Geza Lore ff425369ac
Reduce .rodata footprint of trace initialization (#3250) 
Trace initialization (tracep->decl* functions) used to explicitly pass
the complete hierarchical names of signals as string constants. This
contains a lot of redundancy (path prefixes), does not scale well with
large designs and resulted in .rodata sections (the string constants) in
ELF executables being extremely large.

This patch changes the API of trace initialization that allows pushing
and popping name prefixes as we walk the hierarchy tree, which are
prepended to declared signal names at run-time during trace
initialization. This in turn allows us to emit repeat path/name
components only once, effectively removing all duplicate path prefixes.
On SweRV EH1 this reduces the .rodata section in a --trace build by 94%.

Additionally, trace declarations are now emitted in lexical order by
hierarchical signal names, and the top level trace initialization
function respects --output-split-ctrace.
2021-12-19 15:15:07 +00:00

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$version Generated by VerilatedVcd $end
$date Sat Dec 18 13:32:31 2021 $end
$timescale 1ps $end
$scope module top $end
$var wire 1 W clk $end
$scope module t $end
$var wire 1 W clk $end
$var wire 32 & cyc [31:0] $end
$var wire 8 ' cyc_copy [7:0] $end
$var wire 1 % toggle $end
$var wire 32 ; vlCoverageLineTrace_t_cover_line__102_elsif [31:0] $end
$var wire 32 < vlCoverageLineTrace_t_cover_line__105_elsif [31:0] $end
$var wire 32 = vlCoverageLineTrace_t_cover_line__112_else [31:0] $end
$var wire 32 > vlCoverageLineTrace_t_cover_line__112_if [31:0] $end
$var wire 32 X vlCoverageLineTrace_t_cover_line__119_block [31:0] $end
$var wire 32 # vlCoverageLineTrace_t_cover_line__15_block [31:0] $end
$var wire 32 $ vlCoverageLineTrace_t_cover_line__18_block [31:0] $end
$var wire 32 ( vlCoverageLineTrace_t_cover_line__47_block [31:0] $end
$var wire 32 ) vlCoverageLineTrace_t_cover_line__48_else [31:0] $end
$var wire 32 * vlCoverageLineTrace_t_cover_line__48_if [31:0] $end
$var wire 32 + vlCoverageLineTrace_t_cover_line__52_else [31:0] $end
$var wire 32 , vlCoverageLineTrace_t_cover_line__52_if [31:0] $end
$var wire 32 - vlCoverageLineTrace_t_cover_line__53_else [31:0] $end
$var wire 32 . vlCoverageLineTrace_t_cover_line__53_if [31:0] $end
$var wire 32 / vlCoverageLineTrace_t_cover_line__58_else [31:0] $end
$var wire 32 0 vlCoverageLineTrace_t_cover_line__58_if [31:0] $end
$var wire 32 1 vlCoverageLineTrace_t_cover_line__59_else [31:0] $end
$var wire 32 2 vlCoverageLineTrace_t_cover_line__59_if [31:0] $end
$var wire 32 3 vlCoverageLineTrace_t_cover_line__65_else [31:0] $end
$var wire 32 4 vlCoverageLineTrace_t_cover_line__65_if [31:0] $end
$var wire 32 5 vlCoverageLineTrace_t_cover_line__66_else [31:0] $end
$var wire 32 6 vlCoverageLineTrace_t_cover_line__66_if [31:0] $end
$var wire 32 7 vlCoverageLineTrace_t_cover_line__75_elsif [31:0] $end
$var wire 32 8 vlCoverageLineTrace_t_cover_line__79_elsif [31:0] $end
$var wire 32 9 vlCoverageLineTrace_t_cover_line__83_else [31:0] $end
$var wire 32 : vlCoverageLineTrace_t_cover_line__83_if [31:0] $end
$var wire 32 ] vlCoverageLineTrace_t_cover_line__92_block [31:0] $end
$var wire 32 ^ vlCoverageLineTrace_t_cover_line__93_block [31:0] $end
$var wire 32 _ vlCoverageLineTrace_t_cover_line__96_block [31:0] $end
$var wire 32 ` vlCoverageLineTrace_t_cover_line__97_block [31:0] $end
$scope module a1 $end
$var wire 1 W clk $end
$var wire 1 % toggle $end
$var wire 32 ? vlCoverageLineTrace_t_cover_line__132_block [31:0] $end
$var wire 32 @ vlCoverageLineTrace_t_cover_line__133_else [31:0] $end
$var wire 32 A vlCoverageLineTrace_t_cover_line__133_if [31:0] $end
$var wire 32 B vlCoverageLineTrace_t_cover_line__137_else [31:0] $end
$upscope $end
$scope module a2 $end
$var wire 1 W clk $end
$var wire 1 % toggle $end
$var wire 32 C vlCoverageLineTrace_t_cover_line__132_block [31:0] $end
$var wire 32 D vlCoverageLineTrace_t_cover_line__133_else [31:0] $end
$var wire 32 E vlCoverageLineTrace_t_cover_line__133_if [31:0] $end
$var wire 32 F vlCoverageLineTrace_t_cover_line__137_else [31:0] $end
$upscope $end
$scope module b1 $end
$var wire 1 W clk $end
$var wire 1 % toggle $end
$var wire 32 K vlCoverageLineTrace_t_cover_line__156_block [31:0] $end
$var wire 32 L vlCoverageLineTrace_t_cover_line__158_else [31:0] $end
$var wire 32 b vlCoverageLineTrace_t_cover_line__158_if [31:0] $end
$var wire 32 M vlCoverageLineTrace_t_cover_line__162_else [31:0] $end
$var wire 32 N vlCoverageLineTrace_t_cover_line__162_if [31:0] $end
$var wire 32 O vlCoverageLineTrace_t_cover_line__166_else [31:0] $end
$upscope $end
$scope module b2 $end
$var wire 1 W clk $end
$var wire 1 % toggle $end
$var wire 32 P vlCoverageLineTrace_t_cover_line__156_block [31:0] $end
$var wire 32 Q vlCoverageLineTrace_t_cover_line__158_else [31:0] $end
$var wire 32 c vlCoverageLineTrace_t_cover_line__158_if [31:0] $end
$var wire 32 R vlCoverageLineTrace_t_cover_line__162_else [31:0] $end
$var wire 32 S vlCoverageLineTrace_t_cover_line__162_if [31:0] $end
$var wire 32 T vlCoverageLineTrace_t_cover_line__166_else [31:0] $end
$upscope $end
$scope module o1 $end
$var wire 1 W clk $end
$var wire 1 % toggle $end
$var wire 32 G vlCoverageLineTrace_t_cover_line__220_block [31:0] $end
$var wire 32 H vlCoverageLineTrace_t_cover_line__221_else [31:0] $end
$var wire 32 I vlCoverageLineTrace_t_cover_line__221_if [31:0] $end
$var wire 32 J vlCoverageLineTrace_t_cover_line__224_else [31:0] $end
$var wire 32 a vlCoverageLineTrace_t_cover_line__224_if [31:0] $end
$upscope $end
$scope module t1 $end
$var wire 1 W clk $end
$var wire 1 % toggle $end
$var wire 32 U vlCoverageLineTrace_t_cover_line__187_block [31:0] $end
$var wire 32 Y vlCoverageLineTrace_t_cover_line__191_block [31:0] $end
$var wire 32 Z vlCoverageLineTrace_t_cover_line__194_else [31:0] $end
$var wire 32 [ vlCoverageLineTrace_t_cover_line__194_if [31:0] $end
$var wire 32 V vlCoverageLineTrace_t_cover_line__197_else [31:0] $end
$var wire 32 \ vlCoverageLineTrace_t_cover_line__197_if [31:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
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