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23 lines
480 B
Systemverilog
23 lines
480 B
Systemverilog
// DESCRIPTION: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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process p; // force importing std into top-level namespace
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class C;
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function new;
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if (randomize() != 1) $stop;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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initial begin
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C c = new;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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