mirror of
https://github.com/verilator/verilator.git
synced 2025-04-05 12:12:39 +00:00
17 lines
402 B
Systemverilog
17 lines
402 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2004 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t;
|
|
// verilator_no_inline_module
|
|
initial begin
|
|
case (1'b1) // synopsys_full_case
|
|
1'b0: $stop;
|
|
endcase
|
|
$stop; // Should have failed
|
|
end
|
|
|
|
endmodule
|