mirror of
https://github.com/verilator/verilator.git
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185e5d8f42
IEEE 1800-2017 6.11.3 says these types are unsigned. Until now these types were treated as not having a signedness (NOSIGN), and nodes having these types were later resolved by V3Width to be unsigned. This is a bit problematic when creating nodes of these types after V3Width. Treating these types as unsigned from the get go is fine, and actually improves generated code slightly.
216 lines
14 KiB
XML
216 lines
14 KiB
XML
<?xml version="1.0" ?>
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="<built-in>" language="1800-2017"/>
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<file id="b" filename="<command-line>" language="1800-2017"/>
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<file id="c" filename="input.vc" language="1800-2017"/>
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<file id="d" filename="t/t_xml_flat_vlvbound.v" language="1800-2017"/>
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</files>
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<module_files>
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<file id="d" filename="t/t_xml_flat_vlvbound.v" language="1800-2017"/>
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</module_files>
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<cells>
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<cell fl="d7" loc="d,7,8,7,21" name="$root" submodname="$root" hier="$root"/>
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</cells>
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<netlist>
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<module fl="d7" loc="d,7,8,7,21" name="$root" origName="$root" topModule="1" public="true">
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<var fl="d9" loc="d,9,25,9,28" name="i_a" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_a" public="true"/>
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<var fl="d10" loc="d,10,25,10,28" name="i_b" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="i_b" public="true"/>
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<var fl="d11" loc="d,11,25,11,28" name="o_a" dtype_id="2" dir="output" pinIndex="3" vartype="logic" origName="o_a" public="true"/>
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<var fl="d12" loc="d,12,25,12,28" name="o_b" dtype_id="2" dir="output" pinIndex="4" vartype="logic" origName="o_b" public="true"/>
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<var fl="d9" loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1" vartype="logic" origName="i_a"/>
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<var fl="d10" loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1" vartype="logic" origName="i_b"/>
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<var fl="d11" loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2" vartype="logic" origName="o_a"/>
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<var fl="d12" loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2" vartype="logic" origName="o_b"/>
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<topscope fl="d7" loc="d,7,8,7,21">
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<scope fl="d7" loc="d,7,8,7,21" name="TOP">
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<varscope fl="d9" loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
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<varscope fl="d10" loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
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<varscope fl="d11" loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
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<varscope fl="d12" loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
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<varscope fl="d9" loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1"/>
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<varscope fl="d10" loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1"/>
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<varscope fl="d11" loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2"/>
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<varscope fl="d12" loc="d,12,25,12,28" name="vlvbound_test.o_b" dtype_id="2"/>
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<varscope fl="d15" loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
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<varscope fl="d15" loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
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<varscope fl="d16" loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
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<varscope fl="d17" loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
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<varscope fl="d15" loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
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<varscope fl="d15" loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
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<varscope fl="d16" loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
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<varscope fl="d17" loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
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<assignalias fl="d9" loc="d,9,25,9,28" dtype_id="1">
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<varref fl="d9" loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
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<varref fl="d9" loc="d,9,25,9,28" name="i_a" dtype_id="1"/>
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</assignalias>
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<assignalias fl="d10" loc="d,10,25,10,28" dtype_id="1">
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<varref fl="d10" loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
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<varref fl="d10" loc="d,10,25,10,28" name="i_b" dtype_id="1"/>
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</assignalias>
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<assignalias fl="d11" loc="d,11,25,11,28" dtype_id="2">
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<varref fl="d11" loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
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<varref fl="d11" loc="d,11,25,11,28" name="o_a" dtype_id="2"/>
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</assignalias>
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<assignalias fl="d12" loc="d,12,25,12,28" dtype_id="2">
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<varref fl="d12" loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
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<varref fl="d12" loc="d,12,25,12,28" name="o_b" dtype_id="2"/>
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</assignalias>
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<always fl="d24" loc="d,24,14,24,15">
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<comment fl="d24" loc="d,24,16,24,19" name="Function: foo"/>
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<assign fl="d24" loc="d,24,20,24,23" dtype_id="1">
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<varref fl="d24" loc="d,24,20,24,23" name="i_a" dtype_id="1"/>
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<varref fl="d15" loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
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</assign>
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<assign fl="d18" loc="d,18,11,18,12" dtype_id="3">
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<const fl="d18" loc="d,18,12,18,13" name="32'sh0" dtype_id="4"/>
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<varref fl="d18" loc="d,18,10,18,11" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
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</assign>
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<while fl="d18" loc="d,18,5,18,8">
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<begin>
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</begin>
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<begin>
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<gts fl="d18" loc="d,18,18,18,19" dtype_id="5">
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<const fl="d18" loc="d,18,20,18,21" name="32'sh7" dtype_id="4"/>
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<varref fl="d18" loc="d,18,16,18,17" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
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</gts>
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</begin>
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<begin>
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<assign fl="d19" loc="d,19,14,19,15" dtype_id="5">
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<eq fl="d19" loc="d,19,31,19,33" dtype_id="5">
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<const fl="d19" loc="d,19,34,19,39" name="2'h0" dtype_id="6"/>
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<sel fl="d19" loc="d,19,20,19,21" dtype_id="6">
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<varref fl="d19" loc="d,19,17,19,20" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1"/>
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<sel fl="d19" loc="d,19,22,19,23" dtype_id="7">
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<muls fl="d19" loc="d,19,22,19,23" dtype_id="4">
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<const fl="d19" loc="d,19,23,19,24" name="32'sh2" dtype_id="4"/>
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<varref fl="d19" loc="d,19,21,19,22" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
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</muls>
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<const fl="d19" loc="d,19,22,19,23" name="32'h0" dtype_id="8"/>
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<const fl="d19" loc="d,19,22,19,23" name="32'h4" dtype_id="8"/>
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</sel>
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<const fl="d19" loc="d,19,28,19,29" name="32'sh2" dtype_id="4"/>
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</sel>
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</eq>
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<sel fl="d19" loc="d,19,10,19,11" dtype_id="5">
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<varref fl="d19" loc="d,19,7,19,10" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
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<sel fl="d19" loc="d,19,11,19,12" dtype_id="9">
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<varref fl="d19" loc="d,19,11,19,12" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
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<const fl="d19" loc="d,19,11,19,12" name="32'h0" dtype_id="8"/>
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<const fl="d19" loc="d,19,11,19,12" name="32'h3" dtype_id="8"/>
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</sel>
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<const fl="d19" loc="d,19,10,19,11" name="32'h1" dtype_id="8"/>
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</sel>
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</assign>
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</begin>
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<begin>
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<assign fl="d18" loc="d,18,24,18,26" dtype_id="3">
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<add fl="d18" loc="d,18,24,18,26" dtype_id="8">
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<const fl="d18" loc="d,18,24,18,26" name="32'h1" dtype_id="8"/>
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<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
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</add>
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<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3"/>
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</assign>
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</begin>
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</while>
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<assign fl="d21" loc="d,21,5,21,11" dtype_id="2">
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<varref fl="d21" loc="d,21,12,21,15" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2"/>
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<varref fl="d21" loc="d,21,5,21,11" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
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</assign>
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<assign fl="d24" loc="d,24,14,24,15" dtype_id="2">
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<varref fl="d24" loc="d,24,16,24,19" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2"/>
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<varref fl="d24" loc="d,24,10,24,13" name="o_a" dtype_id="2"/>
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</assign>
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</always>
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<always fl="d25" loc="d,25,14,25,15">
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<comment fl="d25" loc="d,25,16,25,19" name="Function: foo"/>
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<assign fl="d25" loc="d,25,20,25,23" dtype_id="1">
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<varref fl="d25" loc="d,25,20,25,23" name="i_b" dtype_id="1"/>
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<varref fl="d15" loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
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</assign>
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<assign fl="d18" loc="d,18,11,18,12" dtype_id="3">
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<const fl="d18" loc="d,18,12,18,13" name="32'sh0" dtype_id="4"/>
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<varref fl="d18" loc="d,18,10,18,11" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
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</assign>
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<while fl="d18" loc="d,18,5,18,8">
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<begin>
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</begin>
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<begin>
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<gts fl="d18" loc="d,18,18,18,19" dtype_id="5">
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<const fl="d18" loc="d,18,20,18,21" name="32'sh7" dtype_id="4"/>
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<varref fl="d18" loc="d,18,16,18,17" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
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</gts>
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</begin>
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<begin>
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<assign fl="d19" loc="d,19,14,19,15" dtype_id="5">
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<eq fl="d19" loc="d,19,31,19,33" dtype_id="5">
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<const fl="d19" loc="d,19,34,19,39" name="2'h0" dtype_id="6"/>
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<sel fl="d19" loc="d,19,20,19,21" dtype_id="6">
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<varref fl="d19" loc="d,19,17,19,20" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1"/>
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<sel fl="d19" loc="d,19,22,19,23" dtype_id="7">
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<muls fl="d19" loc="d,19,22,19,23" dtype_id="4">
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<const fl="d19" loc="d,19,23,19,24" name="32'sh2" dtype_id="4"/>
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<varref fl="d19" loc="d,19,21,19,22" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
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</muls>
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<const fl="d19" loc="d,19,22,19,23" name="32'h0" dtype_id="8"/>
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<const fl="d19" loc="d,19,22,19,23" name="32'h4" dtype_id="8"/>
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</sel>
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<const fl="d19" loc="d,19,28,19,29" name="32'sh2" dtype_id="4"/>
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</sel>
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</eq>
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<sel fl="d19" loc="d,19,10,19,11" dtype_id="5">
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<varref fl="d19" loc="d,19,7,19,10" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
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<sel fl="d19" loc="d,19,11,19,12" dtype_id="9">
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<varref fl="d19" loc="d,19,11,19,12" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
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<const fl="d19" loc="d,19,11,19,12" name="32'h0" dtype_id="8"/>
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<const fl="d19" loc="d,19,11,19,12" name="32'h3" dtype_id="8"/>
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</sel>
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<const fl="d19" loc="d,19,10,19,11" name="32'h1" dtype_id="8"/>
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</sel>
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</assign>
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</begin>
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<begin>
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<assign fl="d18" loc="d,18,24,18,26" dtype_id="3">
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<add fl="d18" loc="d,18,24,18,26" dtype_id="8">
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<const fl="d18" loc="d,18,24,18,26" name="32'h1" dtype_id="8"/>
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<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
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</add>
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<varref fl="d18" loc="d,18,23,18,24" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3"/>
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</assign>
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</begin>
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</while>
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<assign fl="d21" loc="d,21,5,21,11" dtype_id="2">
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<varref fl="d21" loc="d,21,12,21,15" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2"/>
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<varref fl="d21" loc="d,21,5,21,11" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
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</assign>
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<assign fl="d25" loc="d,25,14,25,15" dtype_id="2">
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<varref fl="d25" loc="d,25,16,25,19" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2"/>
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<varref fl="d25" loc="d,25,10,25,13" name="o_b" dtype_id="2"/>
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</assign>
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</always>
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</scope>
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</topscope>
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<var fl="d15" loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__0__Vfuncout" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__0__Vfuncout"/>
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<var fl="d15" loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__0__val" dtype_id="1" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__0__val"/>
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<var fl="d16" loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__0__ret" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__0__ret"/>
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<var fl="d17" loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__0__i" dtype_id="3" vartype="integer" origName="__Vfunc_vlvbound_test__DOT__foo__0__i"/>
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<var fl="d15" loc="d,15,34,15,37" name="__Vfunc_vlvbound_test.foo__1__Vfuncout" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__1__Vfuncout"/>
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<var fl="d15" loc="d,15,57,15,60" name="__Vfunc_vlvbound_test.foo__1__val" dtype_id="1" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__1__val"/>
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<var fl="d16" loc="d,16,17,16,20" name="__Vfunc_vlvbound_test.foo__1__ret" dtype_id="2" vartype="logic" origName="__Vfunc_vlvbound_test__DOT__foo__1__ret"/>
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<var fl="d17" loc="d,17,13,17,14" name="__Vfunc_vlvbound_test.foo__1__i" dtype_id="3" vartype="integer" origName="__Vfunc_vlvbound_test__DOT__foo__1__i"/>
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</module>
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<typetable fl="a0" loc="a,0,0,0,0">
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<basicdtype fl="d18" loc="d,18,18,18,19" id="5" name="logic"/>
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<basicdtype fl="d19" loc="d,19,34,19,39" id="6" name="logic" left="1" right="0"/>
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<basicdtype fl="d9" loc="d,9,11,9,16" id="1" name="logic" left="15" right="0"/>
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<basicdtype fl="d11" loc="d,11,12,11,17" id="2" name="logic" left="6" right="0"/>
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<basicdtype fl="d17" loc="d,17,5,17,12" id="3" name="integer" left="31" right="0" signed="true"/>
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<basicdtype fl="d19" loc="d,19,10,19,11" id="9" name="logic" left="2" right="0" signed="true"/>
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<basicdtype fl="d19" loc="d,19,11,19,12" id="8" name="logic" left="31" right="0"/>
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<basicdtype fl="d19" loc="d,19,20,19,21" id="7" name="logic" left="3" right="0" signed="true"/>
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<basicdtype fl="d18" loc="d,18,12,18,13" id="4" name="logic" left="31" right="0" signed="true"/>
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</typetable>
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</netlist>
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</verilator_xml>
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