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verilator/test_regress/t/t_lint_repeat_bad.out

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%Warning-WIDTH: t/t_lint_repeat_bad.v:18:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits.
: ... In instance t.sub2
18 | wire [0:0] b = a;
| ^
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to