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https://github.com/verilator/verilator.git
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71 lines
1.7 KiB
C++
71 lines
1.7 KiB
C++
// DESCRIPTION: Verilator: Verilog Test
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//
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// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// clang-format off
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#include "verilatedos.h"
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#include VM_PREFIX_INCLUDE
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#include "Vt_trace_two_b.h"
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#include "verilated.h"
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#ifdef TEST_HDR_TRACE
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# include "verilated_vcd_sc.h"
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#endif
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// clang-format on
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// Compile in place
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#include "Vt_trace_two_b__ALL.cpp"
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// General headers
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#include "verilated.h"
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#include "systemc.h"
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VM_PREFIX* ap;
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Vt_trace_two_b* bp;
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int sc_main(int argc, char** argv) {
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Verilated::debug(0);
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Verilated::traceEverOn(true);
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Verilated::commandArgs(argc, argv);
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sc_signal<bool> clk;
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sc_time sim_time(1100, SC_NS);
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srand48(5);
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ap = new VM_PREFIX{"topa"};
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bp = new Vt_trace_two_b{"topb"};
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ap->clk(clk);
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bp->clk(clk);
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#ifdef TEST_HDR_TRACE
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VerilatedVcdSc* tfp = new VerilatedVcdSc;
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sc_core::sc_start(sc_core::SC_ZERO_TIME);
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ap->trace(tfp, 99);
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bp->trace(tfp, 99);
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tfp->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
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#endif
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{
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clk = false;
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sc_start(10, SC_NS);
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}
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while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
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clk = !clk;
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sc_start(5, SC_NS);
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}
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if (!Verilated::gotFinish()) {
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vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
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}
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ap->final();
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bp->final();
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#ifdef TEST_HDR_TRACE
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if (tfp) tfp->close();
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#endif
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VL_DO_DANGLING(delete ap, ap);
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VL_DO_DANGLING(delete bp, bp);
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return 0;
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}
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