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49 lines
999 B
Systemverilog
49 lines
999 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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);
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class foo;
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int x = 1;
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function int get_x;
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return x;
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endfunction
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function int get_3;
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return 3;
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endfunction
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endclass
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class bar #(type T=foo) extends T;
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endclass
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class baz;
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int x = 2;
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function int get_x;
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return x;
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endfunction
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function int get_4;
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return 4;
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endfunction
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endclass
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bar bar_foo_i;
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bar #(baz) bar_baz_i;
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initial begin
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bar_foo_i = new;
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bar_baz_i = new;
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if (bar_foo_i.get_x() == 1 && bar_foo_i.get_3() == 3 &&
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bar_baz_i.get_x() == 2 && bar_baz_i.get_4() == 4) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$stop;
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end
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end
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endmodule
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