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94 lines
2.3 KiB
Systemverilog
94 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2010 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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`ifdef USE_VPI_NOT_DPI
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//We call it via $c so we can verify DPI isn't required - see bug572
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`else
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import "DPI-C" context function int mon_check();
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`endif
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import "DPI-C" function void dpi_print(input string somestring);
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`ifdef VERILATOR_COMMENTS
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`define PUBLIC_FLAT_RD /*verilator public_flat_rd*/
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`define PUBLIC_FLAT_RW /*verilator public_flat_rw @(posedge clk)*/
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`else
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`define PUBLIC_FLAT_RD
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`define PUBLIC_FLAT_RW
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`endif
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interface intf #(parameter int param `PUBLIC_FLAT_RD = 7);
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localparam int lparam `PUBLIC_FLAT_RD = param + 1;
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logic [7:0] bytesig `PUBLIC_FLAT_RD;
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endinterface
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module t (/*AUTOARG*/
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// Inputs
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input clk `PUBLIC_FLAT_RD,
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// test ports
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input [15:0] testin `PUBLIC_FLAT_RD,
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output [23:0] testout `PUBLIC_FLAT_RW
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);
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`ifdef VERILATOR
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`systemc_header
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extern "C" int mon_check();
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`verilog
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`endif
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reg onebit `PUBLIC_FLAT_RW;
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reg [2:1] twoone `PUBLIC_FLAT_RW;
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reg onetwo [1:2] `PUBLIC_FLAT_RW;
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reg [2:1] fourthreetwoone[4:3] `PUBLIC_FLAT_RW;
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reg [1:0] [1:0] twobytwo `PUBLIC_FLAT_RW;
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int theint `PUBLIC_FLAT_RW;
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integer status;
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`ifdef IVERILOG
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// stop icarus optimizing signals away
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wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3] | twobytwo;
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`endif
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wire subin `PUBLIC_FLAT_RD;
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wire subout `PUBLIC_FLAT_RD;
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sub sub(.*);
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// Test loop
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initial begin
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dpi_print("foo");
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`ifdef VERILATOR
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status = $c32("mon_check()");
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`endif
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`ifdef IVERILOG
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status = $mon_check();
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`endif
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`ifndef USE_VPI_NOT_DPI
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status = mon_check();
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`endif
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if (status!=0) begin
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$write("%%Error: t_vpi_get.cpp:%0d: C Test failed\n", status);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule : t
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module sub #(
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parameter int subparam `PUBLIC_FLAT_RD = 2
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) (
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input subin `PUBLIC_FLAT_RD,
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output subout `PUBLIC_FLAT_RD
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);
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intf the_intf();
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endmodule : sub
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