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d4f7f5297a
Includes `timescale, $printtimescale, $timeformat. VL_TIME_MULTIPLIER, VL_TIME_PRECISION, VL_TIME_UNIT have been removed and the time precision must now match the SystemC time precision. To get closer behavior to older versions, use e.g. --timescale-override "1ps/1ps".
65 lines
1.3 KiB
Systemverilog
65 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under The Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns/1ps
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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time in;
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// verilator lint_off REALCVT
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initial in = 5432109876.543210ns; // Will round to time units
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// verilator lint_on REALCVT
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// This shows time changes when passed between modules with different units
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// See also discussion in uvm_tlm2_time.svh
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ps ps (.*);
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ns ns (.*);
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 60) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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`timescale 1ps/1ps
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module ps
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(input clk,
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input integer cyc,
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input time in);
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always @ (posedge clk) begin
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if (cyc == 10) begin
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$timeformat(-9, 6, "ns", 16);
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$write("%m: Input time %t %d\n", in, in);
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end
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end
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endmodule
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`timescale 1ns/1ps
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module ns
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(input clk,
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input integer cyc,
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input time in);
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always @ (posedge clk) begin
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if (cyc == 20) begin
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$timeformat(-9, 6, "ns", 16);
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$write("%m: Input time %t %d\n", in, in);
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end
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end
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endmodule
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