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2cad22a22a
** Add simulation context (VerilatedContext) to allow multiple fully independent
models to be in the same process. Please see the updated examples.
** Add context->time() and context->timeInc() API calls, to set simulation time.
These now are recommended in place of the legacy sc_time_stamp().
67 lines
1.3 KiB
C++
67 lines
1.3 KiB
C++
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Ted Campbell.
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// SPDX-License-Identifier: CC0-1.0
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#include "Vt_order_multidriven.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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double sc_time_stamp() { return 0; }
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Vt_order_multidriven* vcore;
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VerilatedVcdC* vcd;
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vluint64_t vtime;
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#define PHASE_90
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static void half_cycle(int clk) {
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if (clk & 1) vcore->i_clk_wr = !vcore->i_clk_wr;
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if (clk & 2) vcore->i_clk_rd = !vcore->i_clk_rd;
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vtime += 10 / 2;
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vcore->eval();
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vcore->eval();
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vcd->dump(vtime);
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}
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static void cycle() {
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#ifdef PHASE_90
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half_cycle(1);
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half_cycle(2);
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half_cycle(1);
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half_cycle(2);
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#else
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half_cycle(3);
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half_cycle(3);
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#endif
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}
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int main() {
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const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
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contextp->traceEverOn(true);
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vcore = new VM_PREFIX{contextp.get()};
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vcd = new VerilatedVcdC;
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vcore->trace(vcd, 99);
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vcd->open(VL_STRINGIFY(TEST_OBJ_DIR) "/simx.vcd");
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vcore->i_clk_wr = 0;
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vcore->i_clk_rd = 0;
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for (int i = 0; i < 256; ++i) { //
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cycle();
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}
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vcd->close();
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vcore->final();
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VL_DO_DANGLING(delete vcore, vcore);
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printf("*-* All Finished *-*\n");
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}
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