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25 lines
928 B
Systemverilog
25 lines
928 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2021 by Geza Lore. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// From issue #3096
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module decoder(
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input wire [31:0] instr_i,
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// Making 'a' an output preserves it as a sub-expression and causes a missing clean
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output wire a,
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output wire illegal_instr_o
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);
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/* verilator lint_off WIDTH */
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wire b = ! instr_i[12:5];
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wire c = ! instr_i[1:0];
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wire d = ! instr_i[15:13];
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/* verilator lint_on WIDTH */
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assign a = d ? b : 1'h1;
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assign illegal_instr_o = c ? a : 1'h0;
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endmodule
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