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18 lines
296 B
Systemverilog
18 lines
296 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Wilson Snyder.
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module t (/*AUTOARG*/);
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integer a[];
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string s;
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initial begin
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s = "str";
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a = new [s]; // Bad
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end
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endmodule
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