mirror of
https://github.com/verilator/verilator.git
synced 2025-01-04 05:37:48 +00:00
13 lines
323 B
Verilog
13 lines
323 B
Verilog
// DESCRIPTION: Verilator: Verilog example module
|
|
//
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
// without warranty, 2017 by Wilson Snyder.
|
|
|
|
// See also the EXAMPLE section in the verilator manpage/document.
|
|
module top;
|
|
initial begin
|
|
$display("Hello World!");
|
|
$finish;
|
|
end
|
|
endmodule
|