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93 lines
2.8 KiB
Systemverilog
93 lines
2.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Yutetsu TAKATSUKASA.
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// SPDX-License-Identifier: CC0-1.0
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logic [7:0] should_show_warning_global0 /* verilator split_var */;
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logic [7:0] should_show_warning_global1 [1:0] /* verilator split_var */;
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interface ifs;
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logic [7:0] should_show_warning_ifs0 /* verilator split_var */;
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logic [7:0] should_show_warning_ifs1 [1:0] /* verilator split_var */;
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endinterface
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module t();
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// The following variables can not be splitted. will see warnings.
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real should_show_warning0 /*verilator split_var*/;
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string should_show_warning1 /*verilator split_var*/;
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wire should_show_warning2 /*verilator split_var*/;
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logic [3:0] addr;
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logic [7:0] rd_data0, rd_data1, rd_data2;
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logic [1:0] public_signal /*verilator public*/ /*verilator split_var*/;
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sub0 i_sub0(.addr(addr), .rd_data(rd_data0));
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sub1 i_sub1(.addr(addr), .rd_data(rd_data2));
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sub2 i_sub2;
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sub3 i_sub3;
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ifs i_ifs();
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function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/,
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ref logic [7:0] ref_port /*verilator split_var*/);
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return 0;
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endfunction
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initial begin
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logic [7:0] loop_idx /*verilator split_var*/;
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addr = 0;
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addr = 1;
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i_sub0.cannot_split1[0] = 0;
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i_sub0.cannot_split1[1] = bad_func(addr, rd_data0);
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for (loop_idx = 0; loop_idx < 8'd4; loop_idx = loop_idx + 2) begin
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addr += 1;
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end
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$finish;
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end
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endmodule
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module sub0(input [3:0]addr, output logic [7:0] rd_data);
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logic [7:0] cannot_split0[0:15] /*verilator split_var*/;
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logic [7:0] cannot_split1[0:15] /*verilator split_var*/;
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always_comb
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rd_data = cannot_split0[addr];
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endmodule
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module sub1(input [3:0]addr, output logic [7:0] rd_data);
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genvar cannot_split_genvar /*verilator split_var*/;
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logic [15:0] [8:0] cannot_split /*verilator split_var*/;
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always_comb begin
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logic [8:0] rd_tmp /*verilator split_var*/ = cannot_split[addr];
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rd_data = rd_tmp[{3'b0, addr[0]}+:8];
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end
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endmodule
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module sub2; // from t_bitsel_wire_array_bad.v
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// a and b are arrays of length 1.
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wire a[0:0] /* verilator split_var */ ; // Array of nets
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wire b[0:0] /* verilator split_var */ ;
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assign a = 1'b0; // Only net assignment allowed
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assign b = a[0]; // Only net assignment allowed
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endmodule
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module sub3; // from t_select_bad_range3.v
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logic [7:0] inwires [12:10] /* verilator split_var */;
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wire [7:0] outwires [12:10] /* verilator split_var */;
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assign outwires[10] = inwires[11];
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assign outwires[11] = inwires[12];
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assign outwires[12] = inwires[13]; // must be an error here
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endmodule
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