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61 lines
1.2 KiB
Systemverilog
61 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class ClsZ;
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function new();
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$display("ClsZ::new");
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endfunction
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endclass
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class ClsA;
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function new();
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$display("ClsA::new");
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endfunction
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function void access;
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$display("ClsA::access");
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endfunction
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endclass
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class ClsB;
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static ClsZ z = new;
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function new();
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$display("ClsB::new");
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endfunction
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function void access;
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$display("ClsB::access");
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endfunction
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endclass
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class ClsC;
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// Elaboration will call these
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static ClsA a = new;
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static ClsB b = new;
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function new();
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$display("ClsC::new");
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endfunction
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function void access;
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$display("ClsC::access");
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a = new;
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a.access;
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endfunction
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endclass
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module t (/*AUTOARG*/);
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function void makec;
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ClsC c;
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$display("c = new;");
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c = new;
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$display("c.access;");
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c.access;
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endfunction
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initial begin
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$display("makec;");
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makec;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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