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41 lines
1008 B
Systemverilog
41 lines
1008 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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class Cls #(parameter P = 12);
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bit [P-1:0] member;
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function bit [P-1:0] get_member;
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return member;
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endfunction
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function int get_p;
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return P;
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endfunction
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endclass
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Cls c12;
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Cls #(.P(4)) c4;
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initial begin
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c12 = new;
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c4 = new;
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if (c12.P != 12) $stop;
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if (c4.P != 4) $stop;
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if (c12.get_p() != 12) $stop;
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if (c4.get_p() != 4) $stop;
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// verilator lint_off WIDTH
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c12.member = 32'haaaaaaaa;
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c4.member = 32'haaaaaaaa;
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// verilator lint_on WIDTH
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if (c12.member != 12'haaa) $stop;
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if (c4.member != 4'ha) $stop;
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if (c12.get_member() != 12'haaa) $stop;
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if (c4.get_member() != 4'ha) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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