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35 lines
824 B
Systemverilog
35 lines
824 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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task unit_name;
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$write("unit_name = '%m'\n");
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endtask
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class Cls;
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static task static_name;
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$write("static_name = '%m'\n");
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endtask
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task nonstatic_name;
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$write("nonstatic_name = '%m'\n");
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endtask
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endclass : Cls
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module t (/*AUTOARG*/);
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initial begin
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Cls c;
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c = new;
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$write("t = '%m'\n");
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unit_name();
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$write("Below results vary with simulator.\n");
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// E.g. '$unit.\Cls::static_name '
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// E.g. '$unit_x.Cls.static_name'
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c.static_name();
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c.nonstatic_name();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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