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131 lines
3.5 KiB
Verilog
131 lines
3.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t_inst(/*AUTOARG*/
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// Outputs
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passed,
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// Inputs
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clk, fastclk
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);
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input clk;
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input fastclk;
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output passed; reg passed; initial passed = 0;
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genvar unused;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire o_com; // From b of t_inst_b.v
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wire o_seq_d1r; // From b of t_inst_b.v
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// End of automatics
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integer _mode; // initial _mode=0
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reg na,nb,nc,nd,ne;
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wire ma,mb,mc,md,me;
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wire da,db,dc,dd,de;
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reg [7:0] wa,wb,wc,wd,we;
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wire [7:0] qa,qb,qc,qd,qe;
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wire [5:0] ra;
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wire [4:0] rb;
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wire [29:0] rc;
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wire [63:0] rd;
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reg [5:0] sa;
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reg [4:0] sb;
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reg [29:0] sc;
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reg [63:0] sd;
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reg _guard1; initial _guard1=0;
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wire [104:0] r_wide = {ra,rb,rc,rd};
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reg _guard2; initial _guard2=0;
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wire [98:0] r_wide0 = {rb,rc,rd};
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reg _guard3; initial _guard3=0;
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wire [93:0] r_wide1 = {rc,rd};
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reg _guard4; initial _guard4=0;
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wire [63:0] r_wide2 = {rd};
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reg _guard5; initial _guard5=0;
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wire [168:0] r_wide3 = {ra,rb,rc,rd,rd};
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reg [127:0] _guard6; initial _guard6=0;
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t_inst_a a (
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.clk (clk),
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// Outputs
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.o_w5 ({ma,mb,mc,md,me}),
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.o_w5_d1r ({da,db,dc,dd,de}),
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.o_w40 ({qa,qb,qc,qd,qe}),
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.o_w104 ({ra,rb,rc,rd}),
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// Inputs
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.i_w5 ({na,nb,nc,nd,ne}),
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.i_w40 ({wa,wb,wc,wd,we}),
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.i_w104 ({sa,sb,sc,sd})
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);
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reg i_seq;
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reg i_com;
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wire [15:14] o2_comhigh;
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t_inst_b b (
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.o2_com (o2_comhigh),
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.i2_com ({i_com,~i_com}),
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.wide_for_trace (128'h1234_5678_aaaa_bbbb_cccc_dddd),
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.wide_for_trace_2 (_guard6 + 128'h1234_5678_aaaa_bbbb_cccc_dddd),
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/*AUTOINST*/
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// Outputs
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.o_seq_d1r (o_seq_d1r),
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.o_com (o_com),
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// Inputs
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.clk (clk),
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.i_seq (i_seq),
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.i_com (i_com));
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// surefire lint_off STMINI
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initial _mode = 0;
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always @ (posedge fastclk) begin
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if (_mode==1) begin
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if (o_com !== ~i_com) $stop;
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if (o2_comhigh !== {~i_com,i_com}) $stop;
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end
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end
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always @ (posedge clk) begin
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//$write("[%0t] t_inst: MODE = %0x NA=%x MA=%x DA=%x\n", $time, _mode,
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// {na,nb,nc,nd,ne}, {ma,mb,mc,md,me}, {da,db,dc,dd,de});
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$write("[%0t] t_inst: MODE = %0x IS=%x OS=%x\n", $time, _mode, i_seq, o_seq_d1r);
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if (_mode==0) begin
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$write("[%0t] t_inst: Running\n", $time);
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_mode<=1;
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{na,nb,nc,nd,ne} <= 5'b10110;
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{wa,wb,wc,wd,we} <= {8'ha, 8'hb, 8'hc, 8'hd, 8'he};
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{sa,sb,sc,sd} <= {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210};
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//
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i_seq <= 1'b1;
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i_com <= 1'b1;
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end
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else if (_mode==1) begin
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_mode<=2;
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if ({ma,mb,mc,md,me} !== 5'b10110) $stop;
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if ({qa,qb,qc,qd,qe} !== {8'ha,8'hb,8'hc,8'hd,8'he}) $stop;
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if ({sa,sb,sc,sd} !== {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}) $stop;
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end
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else if (_mode==2) begin
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_mode<=3;
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if ({da,db,dc,dd,de} !== 5'b10110) $stop;
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if (o_seq_d1r !== ~i_seq) $stop;
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//
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$write("[%0t] t_inst: Passed\n", $time);
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passed <= 1'b1;
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end
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if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin
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$write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5);
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$stop;
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end
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end
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// surefire lint_off UDDSDN
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wire _unused_ok = |{1'b1, r_wide0, r_wide1,r_wide2,r_wide3,r_wide};
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endmodule
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