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47 lines
996 B
Verilog
47 lines
996 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2016 by Adrian Wise
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//bug1104
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module t (input clk);
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simple_bus sb_intf(clk);
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simple_bus #(.DWIDTH(16)) wide_intf(clk);
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mem mem(sb_intf.slave);
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cpu cpu(sb_intf.master);
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mem memW(wide_intf.slave);
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cpu cpuW(wide_intf.master);
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endmodule
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interface simple_bus #(AWIDTH = 8, DWIDTH = 8)
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(input logic clk); // Define the interface
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logic req, gnt;
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logic [AWIDTH-1:0] addr;
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logic [DWIDTH-1:0] data;
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modport slave( input req, addr, clk,
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output gnt,
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input data);
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modport master(input gnt, clk,
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output req, addr,
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output data);
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endinterface: simple_bus
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module mem(interface a);
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logic avail;
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always @(posedge a.clk)
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a.gnt <= a.req & avail;
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initial begin
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if ($bits(a.data != 16)) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module cpu(interface b);
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endmodule
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