verilator/test_regress/t/t_trace_packed_struct_fst.out

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$date
Sun Oct 21 21:56:54 2018
$end
$version
fstWriter
$end
$timescale
1ns
$end
$scope module top $end
$var wire 1 ! clk $end
$scope module t $end
$var wire 1 ! clk $end
$var int 32 " cnt $end
$var parameter 96 # v(0) $end
$var parameter 96 $ v(1) $end
$var parameter 96 % v(2) $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
0!
b00000000000000000000000000000000 "
b001100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 #
b001000000000000000000000000000100010000000000000000000000000000100100000000000000000000000000000 $
b000100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 %
#10
b00000000000000000000000000000001 "
1!
#15
0!
#20
1!
b00000000000000000000000000000010 "
#25
0!
#30
1!
b00000000000000000000000000000011 "
#35
0!
#40
1!
b00000000000000000000000000000011 "