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129 lines
4.1 KiB
Perl
Executable File
129 lines
4.1 KiB
Perl
Executable File
#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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use IO::File;
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#use Data::Dumper;
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use strict;
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use vars qw($Self);
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scenarios(simulator => 1);
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my $width = 64*($ENV{VERILATOR_TEST_WIDTH}||4);
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my $vars = 64;
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$Self->{cycles} = ($Self->{benchmark} ? 1_000_000 : 100);
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$Self->{sim_time} = $Self->{cycles} * 10 + 1000;
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sub gen {
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my $filename = shift;
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my $fh = IO::File->new(">$filename");
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$fh->print("// Generated by t_gate_tree.pl\n");
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$fh->print("module t (clk);\n");
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$fh->print(" input clk;\n");
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$fh->print("\n");
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$fh->print(" integer cyc=0;\n");
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$fh->print(" reg reset;\n");
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$fh->print("\n");
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my %tree;
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my $fanin = 8;
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my $stages = int(log($vars)/log($fanin)+0.99999)+1;
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my $result = 0;
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for (my $n=0; $n<$vars; $n++) {
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$result += ($n||1);
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$tree{0}{$n}{$n} = 1;
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my $nl = $n;
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for (my $stage=1; $stage<$stages; $stage++) {
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my $lastn = $nl;
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$nl = int($nl/$fanin);
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$tree{$stage}{$nl}{$lastn} = 1;
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}
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}
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#print Dumper(\%tree);
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$fh->print("\n");
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my $workingset = 0;
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foreach my $stage (sort {$a<=>$b} keys %tree) {
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foreach my $n (sort {$a<=>$b} keys %{$tree{$stage}}) {
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$fh->print( " reg [".($width-1).":0] v${stage}_${n};\n");
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$workingset += int($width/8 + 7);
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}
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}
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$fh->print("\n");
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$fh->print(" always @ (posedge clk) begin\n");
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$fh->print(" cyc <= cyc + 1;\n");
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$fh->print("`ifdef TEST_VERBOSE\n");
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$fh->print(" \$write(\"[%0t] rst=%0x v0_0=%0x v1_0=%0x result=%0x\\n\""
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.", \$time, reset, v0_0, v1_0, v".($stages-1)."_0);\n");
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$fh->print("`endif\n");
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$fh->print(" if (cyc==0) begin\n");
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$fh->print(" reset <= 1;\n");
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$fh->print(" end\n");
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$fh->print(" else if (cyc==10) begin\n");
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$fh->print(" reset <= 0;\n");
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$fh->print(" end\n");
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$fh->print("`ifndef SIM_CYCLES\n");
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$fh->print(" `define SIM_CYCLES 99\n");
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$fh->print("`endif\n");
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$fh->print(" else if (cyc==`SIM_CYCLES) begin\n");
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$fh->print(" if (v".($stages-1)."_0 != ${width}'d${result}) \$stop;\n");
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$fh->print(" \$write(\"VARS=${vars} WIDTH=${width}"
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." WORKINGSET=".(int($workingset/1024))."KB\\n\");\n");
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$fh->print(' $write("*-* All Finished *-*\n");',"\n");
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$fh->print(' $finish;',"\n");
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$fh->print(" end\n");
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$fh->print(" end\n");
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$fh->print("\n");
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for (my $n=0; $n<$vars; $n++) {
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$fh->print(" always @ (posedge clk)"
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." v0_${n} <= reset ? ${width}'d".(${n}||1)." : v0_"
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.((int($n/$fanin)*$fanin) + (($n+1) % $fanin)).";\n");
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}
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foreach my $stage (sort {$a<=>$b} keys %tree) {
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next if $stage == 0;
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$fh->print("\n");
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foreach my $n (sort {$a<=>$b} keys %{$tree{$stage}}) {
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$fh->print(" always @ (posedge clk)"
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." v${stage}_${n} <=");
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my $op = "";
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foreach my $ni (sort {$a<=>$b} keys %{$tree{$stage}{$n}}) {
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$fh->print($op." v".(${stage}-1)."_${ni}");
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$op = " +";
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}
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$fh->print(";\n");
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}
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}
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$fh->print("endmodule\n");
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}
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top_filename("$Self->{obj_dir}/t_gate_tree.v");
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gen($Self->{top_filename});
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compile(
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v_flags2 => ["+define+SIM_CYCLES=$Self->{cycles}",],
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verilator_flags2=>["--stats --x-assign fast --x-initial fast",
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"-Wno-UNOPTTHREADS"],
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);
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execute(
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all_run_flags => ["+verilator+prof+threads+start+100",
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" +verilator+prof+threads+window+2",
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" +verilator+prof+threads+file+$Self->{obj_dir}/profile_threads.dat",
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],
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check_finished => 1,
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);
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ok(1);
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1;
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