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32 lines
619 B
Verilog
32 lines
619 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Jonathon Donaldson.
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package our_pkg;
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typedef enum logic [8-1:0] {
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ADC_IN2IN = 8'h99,
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ADC_IMMED = 8'h88,
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ADC_INDIR = 8'h86,
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ADC_INIDX = 8'h97
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} T_Opcode;
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endpackage : our_pkg
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module t ();
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our our ();
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endmodule
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module our
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import our_pkg::*;
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();
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T_Opcode IR = ADC_IN2IN;
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initial begin
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$write ("%s (%t)\n", IR.name, $realtime);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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