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8127a79cb1
IMPORTANT: Packed arrays are now represented as a single linear vector in Verilated models this may affect packed arrays that are public or accessed via the VPI.
33 lines
680 B
Verilog
33 lines
680 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// A test case for struct signal bit selection.
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//
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// This test is to check that bit selection of multi-dimensional signal inside
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// of a struct works.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jie Xu.
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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typedef struct packed {
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logic [1:0][15:0] channel;
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logic others;
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} buss_t;
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buss_t b;
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reg [7:0] a;
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initial begin
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b = {16'h8765,16'h4321,1'b1};
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a = b.channel[0][8+:8];
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if (a != 8'h43) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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