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56 lines
2.4 KiB
ReStructuredText
.. Copyright 2003-2024 by Wilson Snyder.
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.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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********
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Overview
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********
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Welcome to Verilator!
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The Verilator package converts Verilog [#]_ and SystemVerilog [#]_ hardware
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description language (HDL) designs into a C++ or SystemC model that, after
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compiling, can be executed. Verilator is not a traditional simulator but a
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compiler.
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Verilator is typically used as follows:
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1. The :command:`verilator` executable is invoked with parameters similar
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to GCC or other simulators such as Cadence Verilog-XL/NC-Verilog, or
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Synopsys VCS. Verilator reads the specified SystemVerilog code, lints it,
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optionally adds coverage and waveform tracing support, and compiles the
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design into a source-level multithreaded C++ or SystemC "model". The
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resulting model's C++ or SystemC code is output as .cpp and .h files. This
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is referred to as "Verilating", and the process is "to Verilate"; the
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output is a "Verilated" model.
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2. For simulation, a small user-written C++ wrapper file is required, the
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"wrapper". This wrapper defines the C++ standard function "main()", which
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instantiates the Verilated model as a C++/SystemC object.
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3. The user C++ wrapper, the files created by Verilator, a "runtime
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library" provided by Verilator, and, if applicable, SystemC libraries are
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then compiled using a C++ compiler to create a simulation executable.
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4. The resulting executable will perform the actual simulation during
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"simulation runtime".
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5. If appropriately enabled, the executable may also generate waveform
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traces of the design that may be viewed. It may also create coverage
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analysis data for post-analysis.
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The best place to get started is to try the :ref:`Examples`.
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.. [#] Verilog is defined by the `Institute of Electrical and Electronics
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Engineers (IEEE) Standard for Verilog Hardware Description
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Language`, Std. 1364, released in 1995, 2001, and 2005. The
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Verilator documentation uses the shorthand, e.g., "IEEE 1364-2005",
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to refer to the, e.g., 2005 version of this standard.
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.. [#] SystemVerilog is defined by the `Institute of Electrical and
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Electronics Engineers (IEEE) Standard for SystemVerilog - Unified
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Hardware Design, Specification, and Verification Language`, Standard
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1800, released in 2005, 2009, 2012, 2017, and 2023. The Verilator
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documentation uses the shorthand e.g., "IEEE 1800-2023", to refer to
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the, e.g., 2023 version of this standard.
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