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14 lines
306 B
Verilog
14 lines
306 B
Verilog
// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module library_cell(a);
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input [`WIDTH-1:0] a;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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