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52 lines
1.1 KiB
Systemverilog
52 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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typedef enum logic [1:0] { ZERO, ONE } enum_t;
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typedef struct packed { bit a; } struct_packed_t;
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typedef union packed { bit a; } union_packed_t;
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//IEEE 1800-2023 7.2.1
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// These are all legal
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typedef struct packed {
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enum_t e;
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shortint si;
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int it;
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longint li;
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byte by;
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bit bi;
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logic lo;
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reg rg;
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integer in;
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time tim;
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struct_packed_t sp;
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union_packed_t up;
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bit [1:0][2:0] bit_array;
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} legal_t;
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legal_t legal;
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initial begin
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legal.e = ONE;
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legal.si = 1;
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legal.it = 2;
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legal.li = 3;
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legal.by = 4;
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legal.bi = 1'b1;
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legal.lo = 1'b1;
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legal.rg = 1'b1;
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legal.in = 6;
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legal.tim = 7;
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legal.sp.a = 1'b1;
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legal.up.a = 1'b1;
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legal.bit_array[1][1] = 1'b1;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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