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24 lines
711 B
Systemverilog
24 lines
711 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t (/*AUTOARG*/);
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initial begin
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int res[];
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int a [*] = '{1: 100, 2: 200, 3: 300};
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// TODO results not known to be correct
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res = a.map(el) with (el == 2);
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`checkh(res.size, 3);
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`checkh(res[0], 0);
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`checkh(res[1], 1);
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`checkh(res[2], 0);
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end
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endmodule
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