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d4f7f5297a
Includes `timescale, $printtimescale, $timeformat. VL_TIME_MULTIPLIER, VL_TIME_PRECISION, VL_TIME_UNIT have been removed and the time precision must now match the SystemC time precision. To get closer behavior to older versions, use e.g. --timescale-override "1ps/1ps".
104 lines
1.7 KiB
Systemverilog
104 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under The Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//verilator lint_off REALCVT
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`define testmod(modname) \
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module modname; \
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time t; \
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task check; t = 1ns; $write("%m %0t\n", t); endtask \
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endmodule
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`timescale 1s/1fs
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`testmod(s0)
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`timescale 100ms/1fs
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`testmod(s1)
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`timescale 10ms/1fs
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`testmod(s2)
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`timescale 1ms/1fs
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`testmod(s3)
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`timescale 100us/1fs
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`testmod(s4)
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`timescale 10us/1fs
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`testmod(s5)
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`timescale 1us/1fs
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`testmod(s6)
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`timescale 100ns/1fs
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`testmod(s7)
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`timescale 10ns/1fs
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`testmod(s8)
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`timescale 1ns/1fs
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`testmod(s9)
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`timescale 100ps/1fs
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`testmod(s10)
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`timescale 10ps/1fs
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`testmod(s11)
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`timescale 1ps/1fs
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`testmod(s12)
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`timescale 100 fs/1fs
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`testmod(s13)
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`timescale 10fs/1 fs
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`testmod(s14)
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`timescale 1 fs / 1 fs // Comment
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`testmod(s15)
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module r0;
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timeunit 10ns / 1ns;
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task check; $write("%m %0t\n", $time); endtask
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endmodule
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module r1;
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timeunit 10ns;
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timeprecision 1ns;
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task check; $write("%m %0t\n", $time); endtask
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endmodule
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module t;
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s0 s0();
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s1 s1();
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s2 s2();
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s3 s3();
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s4 s4();
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s5 s5();
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s6 s6();
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s7 s7();
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s8 s8();
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s9 s9();
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s10 s10();
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s11 s11();
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s12 s12();
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s13 s13();
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s14 s14();
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s15 s15();
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r0 r0();
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r1 r1();
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final begin
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s0.check();
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s1.check();
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s2.check();
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s3.check();
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s4.check();
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s5.check();
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s6.check();
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s7.check();
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s8.check();
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s9.check();
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s10.check();
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s11.check();
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s12.check();
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s13.check();
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s14.check();
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s15.check();
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r0.check();
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r1.check();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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