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36 lines
1.0 KiB
Systemverilog
36 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc = 0;
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logic [1:0][27:0] ch01;
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logic [1:0][27:0] ch02;
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logic [1:0][27:0] ch03;
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logic [27:0] ch04[1:0];
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/* verilator lint_off WIDTH */
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always @ (posedge clk) begin
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// LHS is a 2D packed array, RHS is 1D packed or Const. Allowed now.
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ch01 <= {{2{28'd4}}};
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ch02 <= {{2{cyc}}};
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ch03 <= 56'd0;
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// LHS is 1D packed, 1D unpacked, this should never work.
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ch04 <= 56'd0;
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$display("ch01: %0x %0x", ch01[0], ch01[1]);
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$display("ch01: %0x %0x", ch02[0], ch02[1]);
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$display("ch01: %0x %0x", ch03[0], ch03[1]);
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$display("ch01: %0x %0x", ch04[0], ch04[1]);
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end
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/* verilator lint_on WIDTH */
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endmodule
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