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31 lines
518 B
Verilog
31 lines
518 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Wilson Snyder.
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module t (
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input wire CLK,
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output reg RESET
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);
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glbl glbl;
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initial RESET = 1'b1;
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always @ (posedge CLK)
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RESET <= glbl.GSR;
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endmodule
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module glbl();
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`ifdef PUB_FUNC
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wire GSR;
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task setGSR;
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/* verilator public */
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input value;
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GSR = value;
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endtask
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`else
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wire GSR /*verilator public*/;
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`endif
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endmodule
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