mirror of
https://github.com/verilator/verilator.git
synced 2025-05-01 13:06:56 +00:00
d330100542
Prior to this we failed to create implicit nets for inputs of gate primitives, which is required by the standard (IEEE 1800-2017 6.10). Note: outputs were covered due to being modeled as the LHS of assignments, which do create implicit nets. |
||
|---|---|---|
| .. | ||
| t | ||
| .gdbinit | ||
| .gitignore | ||
| CMakeLists.txt | ||
| driver.pl | ||
| input.vc | ||
| input.xsim.vc | ||
| Makefile | ||
| Makefile_obj | ||