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verilator/test_regress/t/t_flag_mmd.v
2020-11-18 22:21:48 -05:00

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Systemverilog

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2016 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
endmodule