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This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
75 lines
1.4 KiB
Systemverilog
75 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Julien Margetts.
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module t (/*AUTOARG*/ reset, a, b, c, en, o1, o2, o3, o4, o5);
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input reset;
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input a;
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input b;
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input c;
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input en;
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output reg o1; // Always assigned
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output reg o2; // "
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output reg o3; // "
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output reg o4; // "
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output reg o5; // Latch
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always_comb
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if (reset)
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begin
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o1 = 1'b0;
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o2 = 1'b0;
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o3 = 1'b0;
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o4 = 1'b0;
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o5 = 1'b0;
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end
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else
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begin
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o1 = 1'b1;
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if (en)
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begin
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o2 = 1'b0;
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if (a)
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begin
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o3 = a;
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o5 = 1'b1;
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end
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else
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begin
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o3 = ~a;
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o5 = a;
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end
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// o3 is not assigned in either path of this if/else
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// but no latch because always assigned above
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if (c)
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begin
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o2 = a ^ b;
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o4 = 1'b1;
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end
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else
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o4 = ~a ^ b;
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o2 = 1'b1;
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end
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else
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begin
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o2 = 1'b1;
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if (b)
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begin
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o3 = ~a | b;
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o5 = ~b;
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end
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else
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begin
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o3 = a & ~b;
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// No assignment to o5, expect Warning-LATCH
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end
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o4 = 1'b0;
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end
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end
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endmodule
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