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109 lines
3.5 KiB
C++
109 lines
3.5 KiB
C++
// DESCRIPTION: Verilator: Verilog example module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2017 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//======================================================================
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// For std::unique_ptr
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#include <memory>
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// Include common routines
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#include <verilated.h>
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// Include model header, generated from Verilating "top.v"
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#include "Vtop.h"
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// Current simulation time (64-bit unsigned)
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vluint64_t main_time = 0;
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// Called by $time in Verilog
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double sc_time_stamp() {
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return main_time; // Note does conversion to real, to match SystemC
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}
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int main(int argc, char** argv, char** env) {
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// This is a more complicated example, please also see the simpler examples/make_hello_c.
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// Prevent unused variable warnings
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if (false && argc && argv && env) {}
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// Create logs/ directory in case we have traces to put under it
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Verilated::mkdir("logs");
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// Set debug level, 0 is off, 9 is highest presently used
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// May be overridden by commandArgs argument parsing
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Verilated::debug(0);
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// Randomization reset policy
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// May be overridden by commandArgs argument parsing
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Verilated::randReset(2);
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// Verilator must compute traced signals
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Verilated::traceEverOn(true);
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// Pass arguments so Verilated code can see them, e.g. $value$plusargs
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// This needs to be called before you create any model
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Verilated::commandArgs(argc, argv);
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// Construct the Verilated model, from Vtop.h generated from Verilating "top.v".
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// Using unique_ptr is similar to "Vtop* top = new Vtop" then deleting at end.
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// "TOP" will be the hierarchical name of the module.
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const std::unique_ptr<Vtop> top{new Vtop};
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// Set Vtop's input signals
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top->reset_l = !0;
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top->clk = 0;
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top->in_small = 1;
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top->in_quad = 0x1234;
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top->in_wide[0] = 0x11111111;
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top->in_wide[1] = 0x22222222;
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top->in_wide[2] = 0x3;
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// Simulate until $finish
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while (!Verilated::gotFinish()) {
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main_time++; // Time passes...
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// Toggle a fast (time/2 period) clock
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top->clk = !top->clk;
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// Toggle control signals on an edge that doesn't correspond
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// to where the controls are sampled; in this example we do
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// this only on a negedge of clk, because we know
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// reset is not sampled there.
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if (!top->clk) {
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if (main_time > 1 && main_time < 10) {
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top->reset_l = !1; // Assert reset
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} else {
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top->reset_l = !0; // Deassert reset
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}
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// Assign some other inputs
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top->in_quad += 0x12;
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}
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// Evaluate model
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// (If you have multiple models being simulated in the same
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// timestep then instead of eval(), call eval_step() on each, then
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// eval_end_step() on each. See the manual.)
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top->eval();
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// Read outputs
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VL_PRINTF("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x"
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" -> oquad=%" VL_PRI64 "x owide=%x_%08x_%08x\n",
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main_time, top->clk, top->reset_l, top->in_quad, top->out_quad, top->out_wide[2],
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top->out_wide[1], top->out_wide[0]);
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}
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// Final model cleanup
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top->final();
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// Coverage analysis (calling write only after the test is known to pass)
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#if VM_COVERAGE
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Verilated::mkdir("logs");
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VerilatedCov::write("logs/coverage.dat");
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#endif
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// Return good completion status
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// Don't use exit() or destructor won't get called
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return 0;
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}
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