mirror of
https://github.com/verilator/verilator.git
synced 2025-01-12 09:37:56 +00:00
c9d6344f2f
A lot of optimizations in DFG assume a DAG, but the more things are representable, the more likely it is that a small cyclic sub-graph is present in an otherwise very large graph that is mostly acyclic. In order to avoid loosing optimization opportunities, we explicitly extract the cyclic sub-graphs (which are the strongly connected components + anything feeing them, up to variable boundaries) and treat them separately. This enables optimization of the remaining input. |
||
|---|---|---|
| .. | ||
| t | ||
| .gdbinit | ||
| .gitignore | ||
| CMakeLists.txt | ||
| driver.pl | ||
| input.vc | ||
| input.xsim.vc | ||
| Makefile | ||
| Makefile_obj | ||