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29 lines
623 B
Systemverilog
29 lines
623 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class uvm_component;
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int x;
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function void set_x();
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x = 1;
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endfunction
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function new();
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if(call_set_return_false());
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endfunction
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function bit call_set_return_false;
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set_x();
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return 0;
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endfunction
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endclass
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module t;
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initial begin
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automatic uvm_component a = new;
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if (a.x != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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