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65 lines
1.2 KiB
Systemverilog
65 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Test different uppercase/lowercase capitalization cases
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class ClsMixed;
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int m;
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int M;
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endclass
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class Clsmixed;
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int m;
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int M;
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endclass
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module ModMixed;
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// verilator no_inline_module
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int m;
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int M;
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endmodule
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module Modmixed;
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// verilator no_inline_module
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int m;
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int M;
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endmodule
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module t(/*AUTOARG*/);
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// verilator no_inline_module
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ModMixed modMixed();
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Modmixed modmixed();
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initial begin
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ClsMixed clsMixed;
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Clsmixed clsmixed;
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clsMixed = new;
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clsMixed.m = 1;
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clsMixed.M = 2;
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clsmixed = new;
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clsmixed.m = 3;
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clsmixed.M = 4;
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if (clsMixed.m != 1) $stop;
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if (clsMixed.M != 2) $stop;
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if (clsmixed.m != 3) $stop;
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if (clsmixed.M != 4) $stop;
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modMixed.m = 1;
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modMixed.M = 2;
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modmixed.m = 3;
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modmixed.M = 4;
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if (modMixed.m != 1) $stop;
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if (modMixed.M != 2) $stop;
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if (modmixed.m != 3) $stop;
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if (modmixed.M != 4) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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