mirror of
https://github.com/verilator/verilator.git
synced 2025-04-05 20:22:41 +00:00
95c4ade718
This patch adds some abstract enums to pass to the trace decl* APIs, so
the VCD/FST specific code can be kept in verilated_{vcd,fst}_*.cc, and
removed from V3Emit*. It also reworks the generation of the trace init
functions (those that call 'decl*' for the signals) such that the scope
hierarchy is traversed precisely once during initialization, which
simplifies the FST writer. This later change also has the side effect of
fixing tracing of nested interfaces when traced via an interface
reference - see the change in the expected t_interface_ref_trace - which
previously were missed.
234 lines
4.4 KiB
Plaintext
234 lines
4.4 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$timescale 1ps $end
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$scope module top $end
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$scope module $unit $end
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$var wire 1 # global_bit $end
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$upscope $end
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$var wire 1 = clk $end
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$scope module t $end
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$var wire 1 = clk $end
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$var wire 32 $ cyc [31:0] $end
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$var wire 2 % v_strp [1:0] $end
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$var wire 4 & v_strp_strp [3:0] $end
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$var wire 2 ' v_unip_strp [1:0] $end
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$var wire 2 ( v_arrp [2:1] $end
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$var wire 4 ) v_arrp_arrp [3:0] $end
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$var wire 4 * v_arrp_strp [3:0] $end
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$var wire 1 > v_arru[1] $end
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$var wire 1 ? v_arru[2] $end
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$var wire 1 @ v_arru_arru[3][1] $end
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$var wire 1 A v_arru_arru[3][2] $end
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$var wire 1 B v_arru_arru[4][1] $end
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$var wire 1 C v_arru_arru[4][2] $end
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$var wire 2 + v_arru_arrp[3] [2:1] $end
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$var wire 2 , v_arru_arrp[4] [2:1] $end
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$var wire 2 - v_arru_strp[3] [1:0] $end
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$var wire 2 . v_arru_strp[4] [1:0] $end
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$var real 64 / v_real $end
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$var real 64 1 v_arr_real[0] $end
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$var real 64 3 v_arr_real[1] $end
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$var wire 64 5 v_str32x2 [63:0] $end
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$var wire 32 7 v_enumed [31:0] $end
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$var wire 32 8 v_enumed2 [31:0] $end
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$var wire 3 9 v_enumb [2:0] $end
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$var wire 6 : v_enumb2_str [5:0] $end
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$var wire 8 D unpacked_array[-2] [7:0] $end
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$var wire 8 E unpacked_array[-1] [7:0] $end
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$var wire 8 F unpacked_array[0] [7:0] $end
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$var wire 1 G LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
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$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end
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$var wire 32 H PARAM [31:0] $end
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$upscope $end
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$scope module p2 $end
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$var wire 32 I PARAM [31:0] $end
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$upscope $end
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$scope module p3 $end
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$var wire 32 J PARAM [31:0] $end
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$upscope $end
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$scope module unnamedblk1 $end
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$var wire 32 ; b [31:0] $end
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$scope module unnamedblk2 $end
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$var wire 32 < a [31:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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