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13 lines
277 B
Systemverilog
13 lines
277 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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class foo;
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task bar;
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int qux;
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qux <= '1;
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endtask
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endclass
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