verilator/test_regress/t/t_unopt_converge_run_bad.pl
Wilson Snyder 8e7267f0e2 With VL_DEBUG, show wires causing convergance errors.
git-svn-id: file://localhost/svn/verilator/trunk/verilator@883 77ca24e4-aefa-0310-84f0-b9a241c72d87
2007-01-31 21:49:13 +00:00

23 lines
577 B
Perl
Executable File

#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2007 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
top_filename("t/t_unopt_converge.v");
compile (
v_flags2 => ['+define+ALLOW_UNOPT'],
);
execute (
fails=>1,
expect=> '%Error: \S+:\d+: Verilated model didn\'t converge',
) if $Last_Self->{v3};
ok(1);
1;