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8738a51449
git-svn-id: file://localhost/svn/verilator/trunk/verilator@870 77ca24e4-aefa-0310-84f0-b9a241c72d87
30 lines
1.1 KiB
Perl
Executable File
30 lines
1.1 KiB
Perl
Executable File
#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
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# $Id$
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# General Public License or the Perl Artistic License.
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top_filename("t/t_unopt_combo.v");
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compile (
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fails=>$Last_Self->{v3},
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expect=>
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'%Warning-UNOPTFLAT: t/t_unopt_combo.v:\d+: Signal unoptimizable: Feedback to clock or circular logic: TOP->v.c
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%Warning-UNOPTFLAT: Use "/\* verilator lint_off UNOPTFLAT \*/" and lint_on around source to disable this message.
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%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: TOP->v.c
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%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: ALWAYS
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%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: TOP->v.b
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%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: ALWAYS
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%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: TOP->v.c
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%Error: Exiting due to '
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);
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execute (
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) if !$Last_Self->{v3};
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ok(1);
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1;
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