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32 lines
616 B
Verilog
32 lines
616 B
Verilog
// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2007 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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`begin_keywords "1364-1995"
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integer signed; initial signed = 1;
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`end_keywords
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`begin_keywords "1364-2001"
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integer bit; initial bit = 1;
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`end_keywords
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`begin_keywords "1364-2005"
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integer final; initial final = 1;
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`begin_keywords "1800-2005"
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final begin
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$write("*-* All Finished *-*\n");
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end
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`end_keywords
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`end_keywords
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initial begin
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$finish;
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end
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endmodule
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