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12 lines
228 B
Verilog
12 lines
228 B
Verilog
// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2006 by Wilson Snyder.
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module t ();
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initial begin
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$stop;
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end
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endmodule
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