verilator/test_regress/t/t_gen_intdot.pl
Wilson Snyder 857ac24ba7 Fix dotted ref signals under generate cells
git-svn-id: file://localhost/svn/verilator/trunk/verilator@837 77ca24e4-aefa-0310-84f0-b9a241c72d87
2006-12-12 18:25:33 +00:00

19 lines
424 B
Perl
Executable File

#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;