verilator/test_regress/t/t_func_lib.pl
Wilson Snyder 7f1b16837e Fix dead modules under generate cells not getting removed
git-svn-id: file://localhost/svn/verilator/trunk/verilator@773 77ca24e4-aefa-0310-84f0-b9a241c72d87
2006-09-01 14:05:20 +00:00

20 lines
468 B
Perl
Executable File

#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
compile (
v_flags2 => ['-v', 't/t_func_lib_sub.v'],
);
execute (
check_finished=>1,
);
ok(1);
1;