verilator/test_regress/t/t_case_genx_bad.v
Wilson Snyder b5b1d94d4a Copyright date update
git-svn-id: file://localhost/svn/verilator/trunk/verilator@864 77ca24e4-aefa-0310-84f0-b9a241c72d87
2007-01-02 22:06:40 +00:00

20 lines
380 B
Verilog

// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005-2007 by Wilson Snyder.
module t (/*AUTOARG*/);
parameter P = 32'b1000;
generate
case (P)
32'b0: initial begin end
32'b1xxx: initial begin end
default: initial begin end
endcase
endgenerate
endmodule