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17 lines
493 B
Systemverilog
17 lines
493 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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initial begin
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int a, b;
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if (std::randomize(a, b) != 1) $stop;
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if (std::randomize(a, b) with { 2 < a; a < 7; b < a; } != 1) $stop;
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if (!(2 < a && a < 7 && b < a)) $stop;
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$write("-*-* All Finished *-*-\n");
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$finish;
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end
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endmodule
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