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2a01365f9b
Due to out of range selects, V3Table attempted to create a table in the constant pool with an 'x' value in it, which caused an internal error. Ensure V3Table behaves the same for out of range selects as the original logic would. There is a related bug #5490, about leaving partially out of range selects in the logic after inserting bounds checks in V3Unknown.
95 lines
2.5 KiB
Systemverilog
95 lines
2.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2014 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// bug823
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [2:0] in = crc[2:0];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [3:0] mask; // From test of Test.v
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wire [3:0] out; // From test of Test.v
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.out (out[3:0]),
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.mask (mask[3:0]),
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// Inputs
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.clk (clk),
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.in (in[2:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {60'h0, out & mask};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n", $time, cyc, crc, out, mask);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end
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else if (cyc<10) begin
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sum <= '0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'ha9d3a7a69d2bea75
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Outputs
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out, mask,
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// Inputs
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clk, in
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);
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input clk;
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input [2:0] in;
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output reg [3:0] out;
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output reg [3:0] mask;
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localparam [15:5] p = 11'h1ac;
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always @(posedge clk) begin
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// verilator lint_off WIDTH
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out <= p[15 + in -: 5];
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// verilator lint_on WIDTH
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end
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always @(posedge clk) begin
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mask[3] <= ((15 + in - 5) < 12);
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mask[2] <= ((15 + in - 5) < 13);
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mask[1] <= ((15 + in - 5) < 14);
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mask[0] <= ((15 + in - 5) < 15);
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end
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endmodule
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